Systems having high speed synchronous interfaces are subject to timing variations in their signals that can limit overall system performance. For example, a system having Single Data Rate (SDR) Synchronous Dynamic Random Access Memory (SDRAM) device typically includes a memory controller, a printed circuit board, and a memory device (SDRAM). Between the memory controller and the memory device there is a synchronous digital communication channel that is generally part of a printed circuit board. Timing variances occur in the signals that are transmitted over the interface due to static and dynamic variations.
Factors causing static timing variations include: length variations in printed circuit board traces among individual traces that make up a common data channel or bus; length variations in wire traces among individual wire traces that make up a common data channel or bus on a semiconductor substrate, such as the memory controller; propagation delay differences between output drivers for individual signals that make up the data channel; and variations in the processing of devices, especially semiconductor devices.
Factors causing dynamic timing variations include differences in temperature and voltage, which affect the drive characteristic of semiconductor device components. For example, a clock distribution network having a plurality of buffers or drivers distributing a specific clock signal will have a varying propagation delay as the drive characteristics of the buffers and drivers varies with temperature and voltage.
All of the dynamic and static factors contribute timing variations and uncertainty in high-speed synchronous interfaces. This is especially problematic for READ cycle where the inability to predict exactly when a READ data from a memory will arrive at the latching elements inside the memory controller. This uncertainty is typically accounted for with timing margin against the setup and hold requirements of the latching device, however, increasing setup and hold margin reduces the maximum clock frequency. Therefore, a method and apparatus that reduces timing variations in a system apparatus would be useful.
One skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures are exaggerated relative to other elements to help to improve understanding of embodiment(s) of the present invention.